Journal of Applied Mathematics

  • J. Appl. Math.
  • Volume 2014, Special Issue (2014), Article ID 197252, 9 pages.

Functional Verification of High Performance Adders in COQ

Qian Wang, Xiaoyu Song, Ming Gu, and Jiaguang Sun

Full-text: Access denied (no subscription detected)

We're sorry, but we are unable to provide you with the full text of this article because we are not able to identify you as a subscriber. If you have a personal subscription to this journal, then please login. If you are already logged in, then you may need to update your profile to register your subscription. Read more about accessing full-text


Addition arithmetic design plays a crucial role in high performance digital systems. The paper proposes a systematic method to formalize and verify adders in a formal proof assistant COQ. The proposed approach succeeds in formalizing the gate-level implementations and verifying the functional correctness of the most important adders of interest in industry, in a faithful, scalable, and modularized way. The methodology can be extended to other adder architectures as well.

Article information

J. Appl. Math., Volume 2014, Special Issue (2014), Article ID 197252, 9 pages.

First available in Project Euclid: 1 October 2014

Permanent link to this document

Digital Object Identifier


Wang, Qian; Song, Xiaoyu; Gu, Ming; Sun, Jiaguang. Functional Verification of High Performance Adders in COQ. J. Appl. Math. 2014, Special Issue (2014), Article ID 197252, 9 pages. doi:10.1155/2014/197252.

Export citation


  • W. A. Hunt Jr. and B. C. Brock, “The verification of a bit-slice ALU,” in Hardware Specification, Verification and Synthesis: Mathematical Aspects, M. Leeser and G. Brown, Eds., vol. 408 of Lecture Notes in Computer Science, pp. 282–306, Springer, New York, NY, USA, 1990.
  • D. Borrione, L. Pierre, and A. Salem, “Formal verification of VHDL descriptions in the prevail environment,” IEEE Design & Test of Computers, vol. 9, no. 2, pp. 42–56, 1992.
  • A. Camilleri, M. Gordon, and T. Melham, Hardware Verification Using Higher-Order Logic, Computer Laboratory, University of Cambridge, Cambridge, UK, 1986.
  • P. Curzon, “Experiences formally verifying a network component,” in Proceedings of the 9th Annual Conference on Computer Assurance (COMPASS '94), Safety, Reliability, Fault Tolerance, Concurrency and Real Time, Security, pp. 183–193, Gaithersburg, Md, USA, July 1994.
  • C. Paulin-Mohring, “Circuits as streams in Coq: verification of a sequential multiplier,” in Types for Proofs and Programs, S. Berardi and M. Coppo, Eds., vol. 1158 of Lecture Notes in Computer Science, pp. 216–230, Springer, Berlin, Germany, 1996.
  • S. Coupet-Grimal and L. Jakubiec, “Certifying circuits in type theory,” Formal Aspects of Computing, vol. 16, no. 4, pp. 352–373, 2004.
  • The Coq Development Team, “The Coq proof assistant, reference manual,” Tech. Rep. version 8.4, INRIA, Roquencourt, France, 2012.
  • T. Braibant, “Coquet: a coq library for verifying hardware,” in Certified Programs and Proofs, J.-P. Jouannaud and Z. Shao, Eds., vol. 7086 of Lecture Notes in Computer Science, pp. 330–345, Springer, Berlin, Germany, 2011.
  • G. J. Milne, Formal Specification and Verification of Digital Systems, McGraw-Hill, New York, NY, USA, 1993.
  • J. T. O'Donnell and G. Rünger, “Functional pearl derivation of a logarithmic time carry lookahead addition circuit,” Journal of Functional Programming, vol. 14, no. 6, pp. 697–713, 2004.
  • F. Liu, Q. Tan, and G. Chen, “Formal proof of prefix adders,” Mathematical and Computer Modelling, vol. 52, no. 1-2, pp. 191–199, 2010.
  • G. Chen, “Formalization of a parameterized parallel adder within the Coq theorem prover,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 1, pp. 149–153, 2010.
  • D. Kapur and M. Subramaniam, “Mechanical verification of adder circuits using rewrite rule laboratory,” Formal Methods in System Design, vol. 13, no. 2, pp. 127–158, 1998.
  • R. Hinze, “An algebra of scans,” in Mathematics of Program Construction, D. Kozen, Ed., vol. 3125 of Lecture Notes in Computer Science, pp. 186–210, Springer, Berlin, Germany, 2004.
  • B. Barras, J. P. Jouannaud, P. Y. Strub, and Q. Wang, “CoQMTU: a higher-order type theory with a predicative hierarchy of universes parametrized by a decidable first-order theory,” in Proceedings of the 26th Annual IEEE Symposium on Logic in Computer Science (LICS '11), pp. 143–151, Ontario, Canada, 2011.
  • Q. Wang and B. Barras, “Semantics of intensional type theory extended with decidable equational theories,” in Computer Science Logic (CSL '13), S. R. D. Rocca, Ed., vol. 23 of Leibniz International Proceedings in Informatics (LIPIcs), pp. 653–667, Schloss Dagstuhl–-Leibniz-Zentrum fuer Informatik, Dagstuhl, Germany, 2013.
  • H. Ling, “High-speed binary adder,” IBM Journal of Research and Development, vol. 25, no. 3, pp. 156–166, 1981.
  • R. Jackson and S. Talwar, “High speed binary addition,” in Proceedings of the Conference Record of the 38th Asilomar Conference on Signals, Systems and Computers, vol. 2, pp. 1350–1353, Asilomar, Calif, USA, November 2004.
  • I. Koren, Computer Arithmetic Algorithms, Universities Press, Hyderabad, India, 2002.
  • P. M. Kogge and H. S. Stone, “A parallel algorithm for the efficient solution of a general class of recurrence equations,” IEEE Transactions on Computers, vol. 2, no. 8, pp. 786–793, 1973. \endinput