## Journal of Applied Mathematics

• J. Appl. Math.
• Volume 2013, Special Issue (2013), Article ID 709071, 7 pages.

### A Transformation-Based Approach to Implication of GSTE Assertion Graphs

#### Abstract

Generalized symbolic trajectory evaluation (GSTE) is a model checking approach and has successfully demonstrated its powerful capacity in formal verification of VLSI systems. GSTE is an extension of symbolic trajectory evaluation (STE) to the model checking of $\omega$-regular properties. It is an alternative to classical model checking algorithms where properties are specified as finite-state automata. In GSTE, properties are specified as assertion graphs, which are labeled directed graphs where each edge is labeled with two labeling functions: antecedent and consequent. In this paper, we show the complement relation between GSTE assertion graphs and finite-state automata with the expressiveness of regular languages and $\omega$-regular languages. We present an algorithm that transforms a GSTE assertion graph to a finite-state automaton and vice versa. By applying this algorithm, we transform the problem of GSTE assertion graphs implication to the problem of automata language containment. We demonstrate our approach with its application to verification of an FIFO circuit.

#### Article information

Source
J. Appl. Math., Volume 2013, Special Issue (2013), Article ID 709071, 7 pages.

Dates
First available in Project Euclid: 9 May 2014

https://projecteuclid.org/euclid.jam/1399645326

Digital Object Identifier
doi:10.1155/2013/709071

Mathematical Reviews number (MathSciNet)
MR3074329

Zentralblatt MATH identifier
1311.68091

#### Citation

Yang, Guowu; Hung, William N. N.; Song, Xiaoyu; Guo, Wensheng. A Transformation-Based Approach to Implication of GSTE Assertion Graphs. J. Appl. Math. 2013, Special Issue (2013), Article ID 709071, 7 pages. doi:10.1155/2013/709071. https://projecteuclid.org/euclid.jam/1399645326

#### References

• J. Yang and C. J. H. Seger, “Generalized symbolic trajectory evaluation,” Technical Report, 2002.
• J. Yang and C. J. H. Seger, “Generalized symbolic trajectory evaluation-abstraction in action,” in FMCAD, vol. 2517, pp. 70–87, 2002.
• J. Yang and C. J. H. Seger, “Introduction to generalized symbolic trajectory evaluation,” IEEE Transactions on VLSI Systems, vol. 11, no. 3, pp. 345–353, 2003.
• J. Yang and C. J. H. Seger, “Compositional specification and model checking in GSTE,” in Computer-Aided Verification, vol. 3114, pp. 216–228, 2004.
• B. Bentley, “High level validation of next generation microprocessors,” in IEEE High Level Design Validation and Test Workshop, 2002.
• A. J. Hu, J. Casas, and J. Yang, “Efficient generation of monitor circuits for GSTE assertion graphs,” in IEEE/ACM International Conference on Computer-Aided Design, pp. 154–159, 2003.
• A. J. Hu, J. Casas, and J. Yang, “Reasoning about GSTE assertion graphs,” in Proceedings of the 12th Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME '03), pp. 170–184, 2003.
• C. T. Chou, “The mathematical foundation of symbolic trajectory evaluation,” in Computer-Aided Verification, vol. 1633, pp. 196–207, 1999.
• C. J. H. Seger and R. E. Bryant, “Formal verification by symbolic evaluation of partially-ordered trajectories,” Formal Methods in System Design, vol. 6, no. 2, pp. 147–190, 1995.
• M. Aagaard, R. B. Jones, and C. J. H. Seger, “Combining theorem proving and trajectory evaluation in an industrial environment,” in Design Automation Conference, pp. 538–541, 1998.
• P. Bjesse, T. Leonard, and A. Mokkedem, “Finding bugs in an $\alpha$ microprocessor using satisfiability solvers,” in Computer-Aided Verification, pp. 454–464, 2001.
• K. L. Nelson, A. Jain, and R. E. Bryant, “Formal verification of a superscalar execution unit,” in Design Automation Conference, pp. 161–167, 1997.
• M. Pandey, R. Raimi, D. L. Beatty, and R. E. Bryant, “Formal verification of PowerPC arrays using symbolic trajectory evaluation,” in Design Automation Conference, pp. 649–654, 1996.
• G. Yang, J. Yang, W. N. N. Hung, and X. Song, “Implication of assertion graphs in GSTE,” in Asia South Pacific Design Automation Conference, pp. 1060–1063, 2005.
• R. Sebastiani, E. Singerman, S. Tonetta, and M. Y. Vardi, “GSTE is partitioned model checking,” in Computer-Aided Verification, vol. 3114, pp. 229–241, Springer, Berlin, Germany, 2004.
• E. Friedgut, O. Kupferman, and M. Vardi, “Büchi complementation made tighter,” in Proceedings of the 2nd International Symposium on Automated Technology for Verification and Analysis, pp. 64–78, 2004, Lecture Notes in Computer Science.
• N. Klarlund, “Progress measures for complementation of $\omega$-automata with applications to temporal logic,” in Proceedings of the 32nd Annual Symposium of Foundations of Computer Science, pp. 358–367, 1991.
• O. Kupferman and M. Y. Vardi, “From complementation to certification,” in Proceedings of the Tools and algorithms for the construction and analysis of systems (TACAS '04), vol. 2988, pp. 591–606, 2004, Lecture Notes on Computer Science.
• R. P. Kurshan, “Complementing deterministic Büchi automata in polynomial time,” Journal of Computer and System Sciences, vol. 35, no. 1, pp. 59–71, 1987.
• M. Michel, “Complementation is more difficult with automata on infinite words,” in CNET, Paris, France, 1988.
• S. Safra, “On the complexity of omega-automata,” in Foundations of Computer Science, pp. 319–327, 1988.
• S. Tasiran, R. Hojati, and R. K. Brayton, “Language containment of non-deterministic omega-automata,” in Proceedings of the IFIP WG 10. 5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME '95), pp. 261–277, Springer, London, UK, 1995.
• J. R. B. Büchi, “On a decision method in restricted second order arithmetic,” in International Congress For Logic, Methodology and Philosophy of Science, pp. 1–12, 1962.
• K. Fisler and R. P. Kurshan, “Verifying vhdl designs with cospan,” in Formal Hardware Verification–-Methods and Systems in Comparison, pp. 206–247, Springer, London, UK, 1997.
• R. P. Kurshan, Computer-Aided Verification of Coordinating Processes, Princeton Series in Computer Science, Princeton University Press, Princeton, NJ, USA, 1994, The automata-theoretic approach.